Common-source Stage Optimization using the Inversion Coefficient
In Open-loop Configuration (Version 3)
Abstract
This notebook shows various ways to minimize the bias current of a simple common-source gain stage. It shows that there is a minimum bias current to achieve a given gain-bandwidth product when accounting for the self-loading parasitic capacitance at the drain. It also extends the analysis to find the minimum bias current to achieve a given gain-bandwidth product and a DC gain at the same time. The notebook is illustrated with several examples including simulations that demonstrate the validity of the theoretical approach.
Licensing
This document is licensed under the Creative Commons License CC BY-NC-SA 
1 Introduction
The schematic of the common-source (CS) stage in open-loop (OL) configuration is shown in Figure 1. To size the transistor according to some specifications on the gain, bandwidth or noise, we need to find the bias current \(I_b\) and the aspect ratio \(W/L\) that satisfies the given specifications. In order to do this, we first need to analyze the circuit in terms of its key features. We will start with a small-signal analysis.
2 Small-signal analysis
The small-signal schematic of the open-loop (OL) common-source (CS) stage of Figure 1 is shown in Figure 2. It is straightforward to show that the transfer function is given by \[\begin{equation} A(s) \triangleq \frac{\Delta V_{out}}{\Delta V_{in}} = A_{dc} \cdot \frac{1-s/\omega_z}{1+s/\omega_p} \end{equation}\] where \[\begin{align} A_{dc} &= -G_m \cdot R_{ds},\\ \omega_z &= \frac{G_m}{C_F},\\ \omega_p &= \frac{1}{R_{ds}\,C_{out}}, \end{align}\] with \(A_{dc} = -G_m \cdot R_{ds}\) the DC voltage gain, \(\omega_z\) the zero (in the right half plan), \(\omega_p\) the pole and \(C_{out}=C_L+C_F\) the total load capacitance at the output node including the feedback capacitance. The gain-bandwidth product (\(GBW\)) or unity gain frequency (\(\omega_u\)) is then given by \[\begin{equation} GBW = \omega_u = |A_{dc}| \cdot \omega_p = \frac{G_m}{C_{out}}. \end{equation}\]
As illustrated in Figure 3, the gain magnitude at high frequency will settle to \[\begin{equation} \lim_{s \to \infty} A(s) = \frac{C_F}{C_L+C_F}, \end{equation}\] and the phase will turn to \(-180^{\circ}\) because of the positive zero.
3 Minimum current for a given transconductance
In this section we want to answer the following question:
Question
What is the minimum current \(I_b\) and transistor size (aspect ratio \(W/L\)) in order for the OL CS gain stage to achieve a given transconductance?
To answer this question we first rewrite the current as \[\begin{equation} I_b = I_{spec\Box} \cdot \frac{W}{L} \cdot IC \end{equation}\] and the transconductance as \[\begin{equation} G_m = \frac{I_{spec\Box}}{n U_T} \cdot \frac{W}{L} \cdot g_{ms}(IC), \end{equation}\] where \(g_{ms}(IC)\) is the normalized source transconductance which only depends on \(IC\) according to \[\begin{equation} g_{ms} \triangleq \frac{G_{ms}}{G_{spec}} = \frac{n\,G_m}{G_{spec}} = \frac{\sqrt{4 IC+1}-1}{2} \end{equation}\] for a long-channel transistor and \[\begin{equation} g_{ms} = \frac{\sqrt{4 IC+1+(\lambda_C\,IC)^2}-1}{2+\lambda_c^2\,IC} \end{equation}\] for a short-channel transistor accounting for velocity saturation with parameter \(\lambda_c\).
We then need to solve the following set of equation for \(I_b\) and \(W/L\) \[\begin{align} G_m &= \frac{I_{spec\Box}}{n U_T} \cdot \frac{W}{L} \cdot g_{ms}(IC),\\ I_b &= I_{spec\Box} \cdot \frac{W}{L} \cdot IC. \end{align}\]
This leads to the following normalized results \[\begin{align} i_b &\triangleq \frac{I_b}{G_m \cdot n U_T} = \frac{IC}{g_{ms}},\\ AR &\triangleq \frac{W}{L} \cdot \frac{I_{spec\Box}}{G_m \cdot n U_T} = \frac{1}{g_{ms}}. \end{align}\] \(i_b\) and \(AR\) are plotted below for various values of \(\lambda_c\)
From Figure 4, we see that we can reduce the current \(i_b\) when moving from strong inversion to moderate inversion reaching a minimum in weak inversion. The loss of transconductance resulting from a reduction of \(IC\) is compensated by an increase of \(W/L\) as shown by the blue curves, resulting in a very large transistor and a drastic area increase. Moderate inversion turns out to be a good trade-off between low current and acceptable area for achieving a given transconductance.
4 Minimum current for a given gain-bandwidth product (no self-loading)
We now will answer the question:
Question
What is the minimum bias current to achieve a given gain-bandwidth product for a given load capacitance neglecting the effect of self-loading?
We first rewrite the gain-bandwidth as \[\begin{equation} \omega_u = \frac{G_m}{C_L} = \omega_L \cdot \frac{W}{L} \cdot g_{ms}, \end{equation}\] where \[\begin{equation} \omega_L \triangleq \frac{I_{spec\Box}}{n U_T \cdot C_{out}}. \end{equation}\]
To answer this question we need to solve the following set of equations for \(I_b\) and \(W/L\) \[\begin{align} \omega_u &= \omega_L \cdot \frac{W}{L} \cdot g_{ms},\\ G_m &= \frac{I_{spec\Box}}{n U_T} \cdot \frac{W}{L} \cdot g_{ms}(IC),\\ I_b &= I_{spec\Box} \cdot \frac{W}{L} \cdot IC. \end{align}\] Since the load capacitance \(C_L\) is assumed constant, the problem is similar to imposing a given transconductance With a slightly different normalization we get the same normalized functions as before \[\begin{align} i_b &\triangleq \frac{I_b}{G_m \cdot n U_T} \cdot \frac{1}{\Omega} = \frac{IC}{g_{ms}},\\ AR &\triangleq \frac{W}{L} \cdot \frac{1}{\Omega} = \frac{1}{g_{ms}}. \end{align}\] with \[\begin{equation} \Omega \triangleq \frac{\omega_u}{\omega_L}. \end{equation}\]
A different normalization reduces to the same trade-off than constant \(G_m\) and hence the normalized bias current \(i_b\) and aspect \(AR\) are identical to the one plotted in Figure 4 for various values of \(\lambda_c\). Moderate inversion again turns out to be a good trade-off between low current and acceptable area for achieving a given gain-bandwidth product.
When moving to moderate and weak inversion, the transistor can become very large. The parasitic capacitance at the transistor drain can then no more be ignored. We will analyze the impact of self-loading in the next section.
5 Minimum current for a given gain-bandwidth product including self-loading (long-channel)
5.1 Analysis
When optimizing the OL CS amplifier for low current consumption, the transistor is often biased in moderate or even weak inversion leading to a large transistor and therefore an increased output capacitance due to the self-loading from the parasitic capacitances connected to the drain. We now want to answer the following question:
Question
What is the minimum bias current \(I_b\) and transistor size (aspect ratio \(W/L\)) in order for the OL CS gain stage to achieve a given gain-bandwidth product accounting for the effect of self-loading?
As shown in Figure 5, the self-loading capacitances include the junction capacitance at the drain \(C_{BDj}\) and the feedback capacitance \(C_F\). The junction capacitance \(C_{BDj}\) is given by \[\begin{equation} C_{BDj} = 2 H_{dif} \cdot W \cdot C_J + 2(2 H_{dif}+W) \cdot C_{JSW} = 4 H_{dif} \cdot C_{JSW} + 2(H_{dif} \cdot C_J + C_{JSW}) \cdot W \end{equation}\] where \(C_J\) is the bottom junction capacitance per area, \(C_{JSW}\) is the side-wall capacitance per unit length and \(H_{dif}\) is the half minimum diffusion width, which is imposed by the layout rules. Of course the junction capacitances per area and per length \(C_J\) and \(C_{JSW}\) are bias dependent since they depend on the drain-to-bulk voltage, but we consider their highest value obtained for a zero drain-to-bulk voltage (worst case).
Since the transistor is biased in saturation, the intrinsic gate-to-drain capaciatnce \(C_{GDi}\) is negligible. The feedback capacitance is therefore due to the extrinsic capacitance which given by \[\begin{equation} C_F = C_{GDe} \cdot W, \end{equation}\] where \(C_{GDe}\) is the extrinsic capacitance per unit width which includes the overlap and fringing field capacitance and is given by \[\begin{equation} C_{GDe} = C_{GDo} + C_{GDf}. \end{equation}\] where \(C_{GDo}\) is the overlap capacitance per unit width and \(C_{GDf}\) is the fringing field capacitance per unit width.
Note
Note that the fringing field capacitance per unit width is ignored in this 180 nm technology but may become of the same order of magnitude than the overlap capacitance per unit width in more advanced technologies.
The total transistor parasitic capacitance at the drain can then be written as \[\begin{equation} C_D = C_{D0} + C_{DW} \cdot W. \end{equation}\] with \[\begin{align} C_{D0} &= 4 H_{dif} \cdot C_{JSW},\\ C_{DW} &= 2(H_{dif} \cdot C_J + C_{JSW}) + C_{GDe}. \end{align}\] The part \(C_{D0}\) of the total parasitic capacitance at the drain \(C_D\) that doesn’t scale with \(W\) needs to be added to \(C_{L0}\) \[\begin{equation} C_L = C_{L0} + C_{D0}. \end{equation}\]
In order to achieve a certain bandwidth we need to have a certain transconductance for a certain load capacitance. In order to maximize the current efficiency, we should bias the transistor in weak inversion. This leads to a large transistor and therefore large parasitic capacitances which will impact the bandwidth. Imposing the bandwidth, at some point the capacitance becomes so large that it is no more possible to achieve the required transconductance in weak inversion for the desired bandwidth.
Question
Does this mean that there is a minimum current for the OL CS amplifier to achieve a certain gain-bandwidth product?
To answer this question we need to solve the following set of equations for \(I_b\) and \(W\) assuming a given length \(L\) \[\begin{align} \omega_u &= \frac{G_m}{C_{out}},\\ G_m &= \frac{I_{spec\Box}}{n U_T} \cdot \frac{W}{L} \cdot g_{ms}(IC),\\ C_{out} &= C_L + C_{DW} \cdot W,\\ I_b &= I_{spec\Box} \cdot \frac{W}{L} \cdot IC. \end{align}\]
Solving for \(I_b\) and \(W/L\) leads to the following normalized solutions \[\begin{align} i_b &\triangleq \frac{I_b}{I_{norm}} = \frac{IC}{g_{ms}(IC) - \Theta},\\ AR &\triangleq \frac{W/L}{\Omega} =\frac{1}{g_{ms} - \Theta}, \end{align}\] where \[\begin{align} I_{norm} &\triangleq I_{spec\Box} \cdot \Omega = n\,U_T \cdot C_L \cdot \omega_u,\\ \Omega &\triangleq \frac{\omega_u}{\omega_L},\\ \omega_L &\triangleq \frac{I_{spec\Box}}{n U_T \cdot C_L},\\ \Theta &\triangleq \frac{\omega_u}{\omega_W},\\ \omega_W &\triangleq \frac{I_{spec\Box}}{n U_T \cdot C_{DW} \cdot L} = \frac{I_{spec}}{n U_T \cdot C_{DW} \cdot W}. \end{align}\]
Note
The normalization current \(I_{norm}\) corresponds to the drain current required to achieve a unity gain frequency \(\omega_u\) in deep weak inversion with a constant load capacitance equal to \(C_L = C_{L0} + C_{D0}\), ignoring the part that is scaling with \(W\).
The normalization frequency \(\omega_L\) corresponds to the unity gain frequency of a square transistor (i.e. with equal width and length \(W=L\)) biased at an inversion coefficient \(IC =\) 2 for which the normalized source transconductance \(g_{ms}\) is equal to 1 and which is loaded only by a capacitance \(C_L = C_{L0} + C_{D0}\), ignoring the part that is scaling with \(W\).
The normalization frequency \(\omega_W\) can be understood as the unity gain frequency of a very wide transistor for which the load capacitance is then dominated by the self-loading capacitance \(W\,C_{DW}\) and biased at an inversion coefficient \(IC =\) 2 for which the normalized source transconductance \(g_{ms}\) is equal to 1 \[\begin{equation} \frac{G_m}{W\,C_{DW}} = \frac{I_{spec}\,g_{ms}(IC=2)}{n U_T\,C_{DW}\,W} = \frac{I_{spec\Box}\,W/L}{n U_T\,C_{DW}\,W} = \frac{I_{spec\Box}}{n U_T\,C_{DW}\,L}. \end{equation}\]
The normalized current \(i_b\) and normalized aspect ratio \(AR\) are plotted in Figure 6 for three values of parameter \(\Theta\). The normalized current \(i_b\) is plotted alone in Figure 7 versus \(IC\) for more values of \(\Theta\).
From Figure 6 and Figure 7, we clearly see that there is a minimum current for a given value of parameter \(\Theta\). We can find the optimum inversion coefficient \(IC_{opt}\) which is given by \[\begin{equation}\label{eqn:icopt} IC_{opt} = \left(\sqrt{\Theta \cdot (1+\Theta)} + \Theta + \frac{1}{2}\right)^2 - \frac{1}{4} = 2 \Theta \cdot (1+\Theta) + (1+2\Theta) \cdot \sqrt{\Theta \cdot (1+\Theta)}. \end{equation}\] For \(\Theta \ll 1\), \(\eqref{eqn:icopt}\) reduces to \[\begin{equation} IC_{opt} \cong 2 \Theta + \sqrt{\Theta}. \end{equation}\]
From the above figure we also see that there is a minimum inversion coefficient \(IC_{lim}\) below which the desired gain-bandwidth product \(GBW\) can no more be achieved \[\begin{equation} IC_{lim} = \Theta \cdot (1+\Theta) \cong \Theta, \end{equation}\] which is about equal to \(\Theta\) for small values of \(\Theta\).
The optimum normalized current is given by \[\begin{equation}\label{eqn:ibopt} i_{bopt} \triangleq i_b(IC_{opt}) = 1 + 2\Theta +2\sqrt{\Theta \cdot (1+\Theta)}. \end{equation}\]
Parameter \(\Theta\) can be eliminated from equations \(\eqref{eqn:ibopt}\) and \(\eqref{eqn:icopt}\) resulting in an expression of \(i_{bopt}\) in terms of \(IC_{opt}\) \[\begin{equation} i_{bopt} = \sqrt{4 IC_{opt} + 1} \end{equation}\] which is plotted as a dashed red line in Figure 6 and Figure 7.
The optimum bias current \(I_{bopt}\) is then simply calculated as \[\begin{equation}\label{eqn:} I_{bopt} = I_{norm} \cdot i_{bopt}. \end{equation}\]
The optimum current also corresponds an optimum transistor width \(W\) and hence and optimum normalized \(W/L\) given by \[\begin{equation}\label{eqn:aropt} AR_{opt} \triangleq AR(IC_{opt}) = \frac{1}{\sqrt{\Theta \cdot (1+\Theta)}}. \end{equation}\] As above, parameter \(\Theta\) can be eliminated between equations \(\eqref{eqn:icopt}\) and \(\eqref{eqn:aropt}\) giving an expression of \(AR_{opt}\) in terms of \(IC_{opt}\) \[\begin{equation} AR_{opt} = \frac{\sqrt{4 IC_{opt} + 1}}{IC_{opt}}, \end{equation}\] which is plotted as a dashed red line in Figure 8.
The optimum aspect ratio is then calculated as \[\begin{equation} \left.\frac{W}{L}\right|_{opt} = AR_{opt} \cdot \Omega \end{equation}\]
We see from Figure 8 that the transistor width increases first as \(1/\sqrt{IC}\) in strong inversion and then as \(1/IC\) in weak inversion making the transistor quickly very large until \(IC\) reaches \(IC_{lim}\) where the width becomes infinity. The dots correspond to the \(AR\) obtained for \(IC_{opt}\).
The optimum parameters \(IC_{opt}\), \(i_{bopt}\) and \(AR_{opt}\) are plotted versus \(\Theta\) in Figure 9. We can see that the optimum inversion coefficient is always located in moderate or eventually weak inversion.
We now will illustrate the above analysis with a practical example.
5.2 Design example
5.2.1 Design
We want to size a CS SC amplifier for the specifications given in Table 1. We need to find the minimum current and size the transistor to achieve this specs. We will design the amplifier for a generic 180nm bulk CMOS process. The physical parameters are given in Table 2, the global process parameters in Table 3 and finally the MOSFET parameters in Table 4.
| Specification | Symbol | Value | Unit |
|---|---|---|---|
| Gain bandwidth product | \(GBW\) | 100 | \(MHz\) |
| Load capacitance | \(C_{{L0}}\) | 20 | \(fF\) |
| Transistor length | \(L\) | 1 | \(\mu m\) |
| Parameter | Value | Unit |
|---|---|---|
| \(T\) | 300 | \(K\) |
| \(U_T\) | 25.875 | \(mV\) |
| Parameter | Value | Unit |
|---|---|---|
| \(V_{DD}\) | 1.8 | \(V\) |
| \(C_{ox}\) | 8.443 | \(\frac{fF}{\mu m^2}\) |
| \(W_{min}\) | 200 | \(nm\) |
| \(L_{min}\) | 180 | \(nm\) |
| Parameter | NMOS | PMOS | Unit |
|---|---|---|---|
| sEKV parameters | |||
| \(n\) | 1.27 | 1.31 | - |
| \(I_{{spec\Box}}\) | 715 | 173 | \(nA\) |
| \(V_{{T0}}\) | 0.455 | 0.445 | \(V\) |
| \(L_{{sat}}\) | 26 | 36 | \(nm\) |
| \(\lambda\) | 15 | 20 | \(\frac{{V}}{{\mu m}}\) |
| Overlap capacitances parameters | |||
| \(C_{{GDo}}\) | 0.366 | 0.329 | \(\frac{{fF}}{{\mu m}}\) |
| \(C_{{GSo}}\) | 0.366 | 0.329 | \(\frac{{fF}}{{\mu m}}\) |
| \(C_{{GBo}}\) | 0 | 0 | \(\frac{{fF}}{{\mu m}}\) |
| Junction capacitances parameters | |||
| \(C_J\) | 1 | 1.121 | \(\frac{{fF}}{{\mu m^2}}\) |
| \(C_{{JSW}}\) | 0.2 | 0.248 | \(\frac{{fF}}{{\mu m}}\) |
| Flicker noise parameters | |||
| \(K_F\) | 8.1e-24 | 6.8e-23 | \(J\) |
| \(AF\) | 1 | 1 | - |
| \(\rho\) | 0.05794 | 0.4828 | \(\frac{{V \cdot m^2}}{{A \cdot s}}\) |
| Matching parameters | |||
| \(A_{{VT}}\) | 5 | 5 | \(mV \cdot \mu m\) |
| \(A_{{\beta}}\) | 1 | 1 | \(\% \cdot \mu m\) |
| Source and drain sheet resistance parameter | |||
| \(R_{{sh}}\) | 600 | 2386 | \(\frac{{\Omega}}{{\mu m}}\) |
| Width and length parameters | |||
| \(\Delta W\) | 39 | 54 | \(\,nm\) |
| \(\Delta L\) | -76 | -72 | \(\,nm\) |
For the chosen technology we get \(C_{DW} =\) 1.167 \(fF/\mu m\) and we get \(C_{D0} =\) 0.160 \(fF\). The total load capacitance that does not scale with \(W\) is now \(C_L =\) 20.160 \(fF\).
We can now calculate all the parameters which are summarized in Table 5.
| Parameter | Value | Unit |
|---|---|---|
| \(C_{{DW}}\) | 1.167 | \(fF/\mu m\) |
| \(C_{{D0}}\) | 0.16 | \(fF\) |
| \(C_{{L0}}\) | 20 | \(fF\) |
| \(C_L\) | 20.16 | \(fF\) |
| \(I_{{norm}}\) | 417 | \(nA\) |
| \(\Omega\) | 0.583 | - |
| \(f_L\) | 171.589 | \(MHz\) |
| \(f_W\) | 2.965 | \(GHz\) |
| \(\Theta\) | 0.03372 | - |
| \(IC_{{opt}}\) | 0.269 | - |
| \(i_{{b,opt}}\) | 1.441 | - |
| \(I_{{b,opt}}\) | 600 | \(nA\) |
| \(AR_{{opt}}\) | 5.356 | - |
| \(\left(W/L\right)_{{opt}}\) | 3.121 | - |
| \(W_{{opt}}\) (effective width) | 2.88 | \(\mu m\) |
| \(L_{{eff}}\) (effective length) | 924 | \(nm\) |
| \(W\) (drawn width) | 2.85 | \(\mu m\) |
| \(L\) (drawn length) | 1 | \(\mu m\) |
| \(G_{{m,opt}}\) | 14.955 | \(\mu A/V\) |
| \(C_{{D,opt}}\) | 3.364 | \(fF\) |
| \(C_F\) | 1.057 | \(fF\) |
| \(C_{{out}}\) | 23.524 | \(fF\) |
| \(f_z\) | 2.252 | \(GHz\) |
| \(A_{{dc}}\) | 50.762 | \(dB\) |
We see that the optimum inversion coefficient is equal to \(IC_{opt} =\) 0.269 which means that the transistor is biased in moderate inversion. The optimum current is the \(I_{bopt} =\) 600 \(nA\).
The transistor size resulting from the design are summarized in Table 6. The large- and small-signal parameters are summarized in Table 7 and Table 8.
| Transistor | \(W\;[\mu m]\) | \(L\;[\mu m]\) | \(W_{eff}\;[\mu m]\) | \(L_{eff}\;[\mu m]\) | \(W_{eff}/L_{eff}\;[-]\) |
|---|---|---|---|---|---|
| M1 | 2.88 | 1.00 | 2.92 | 0.924 | 3.164 |
| M2 | 2.88 | 1.00 | 2.92 | 0.924 | 3.164 |
| Transistor | \(I_D\;[nA]\) | \(I_{{spec}}\;[\mu A]\) | \(IC\) | \(V_G-V_{{T0}}\;[mV]\) | \(V_{{DSsat}}\;[mV]\) |
|---|---|---|---|---|---|
| M1 | 600 | 2262 | 0.265 | -22.137 | 107 |
| M2 | 600 | 2262 | 0.265 | -22.137 | 107 |
| Transistor | \(G_{{spec}}\;[\mu A/V]\) | \(G_{{ms}}\;[\mu A/V]\) | \(G_m\;[\mu A/V]\) | \(G_{{ds}}\;[nA/V]\) | \(\gamma_n\) |
|---|---|---|---|---|---|
| M1 | 87.421 | 19.052 | 14.985 | 40.026 | 0.674 |
| M2 | 87.421 | 19.052 | 14.985 | 40.026 | 0.674 |
5.2.2 Simulations
The theoretical results can be validated by comparing them to the results obtained from simulations performed with ngspice. The cells below will run the simulations with ngspice. In order to run the simulations you need to have ngspice installed. Please refer to the ngspice instructions.
Note
The simulations are performed with ngspice [1] using the EKV 2.6 compact model [2]. For ngspice, we use the original Verilog-A implementation of EKV 2.6 [3] modified by C. Enz to get the operating point informations and available on the Gitub va-models site provided by D. Warning at [4]. The parameters correspond to a generic 180 nm bulk CMOS process [5].
Before running the AC simulation, we first need to check the quiescent voltages and currents and the operating point by running an .OP simulation. The node voltages are extracted from the .ic file and presented in Table 9.
| Node | Voltage |
|---|---|
| vdd | 1.8 |
| in | 0.447093 |
| out | 0.447093 |
| 1 | 0.447093 |
| 2 | 0.447093 |
The large-signal transistor bias information and the small-signal parameters extracted from the simulation are given in Table 10 and Table 11, respectively. We see that their values are very close to the theoretical values given in Table 6 and Table 7.
| Transistor | \(I_D\;[nA]\) | \(I_{spec}\;[\mu A]\) | \(IC\) | \(n\) | \(V_{Dsat}\;[mV]\) |
|---|---|---|---|---|---|
| M1 | 600 | 2.246 | 0.267 | 1.27 | 130 |
| M2 | 600 | 2.246 | 0.267 | 1.27 | 130 |
| Transistor | \(n\) | \(G_{ms}\;[\mu A/V]\) | \(G_m\;[\mu A/V]\) | \(G_{mb}\;[\mu A/V]\) | \(G_{ds}\;[nA/V]\) |
|---|---|---|---|---|---|
| M1 | 1.27 | 18.936 | 14.698 | 4.203 | 34.245 |
| M2 | 1.27 | 18.936 | 14.698 | 4.203 | 34.245 |
The simulated transfer function is shown in Figure 12 and compared to the theoretical transfer function of Figure 10.
From Figure 12 we see that the simulation matches the theoretical estimation very well, at least below the \(GBW\). The simulated \(GBW\) and DC gain are slightly higher than the target. We observe a discrepancy at higher frequency with a simulated zero that is about two times lower than the theoretical estimation. This is due to a larger feedback capacitance. This is actually coming from the fact that we have ignored the transcapacitance \(C_m\) in the small-signal analysis. In the quasi-static (QS) circuit of the MOS transistor, the transconductance needs to be replaced by the a transadmittance \(Y_m\) given by \[\begin{equation} Y_m = G_m - s\,C_m \end{equation}\] where \(C_m\) is the gate transcapacitance given by \[\begin{equation} C_m = C_{OX} \cdot c_m \end{equation}\] where \(C_{OX} \triangleq W\,L\,C_{ox}\) and \(c_m\) is the normalized gate transcapacitance given by [6] \[\begin{equation} c_m = \frac{q_s-q_d}{15}\;\frac{4 q_s^2+4 q_d^2+12 q_s q_d+10 q_s+10 q_d+5}{(q_s+q_d+q)^3}, \end{equation}\] which in saturation (\(q_d=0\)) reduces to \[\begin{equation} c_{m_{sat}} \cong \frac{4 q_s^2+10 q_s+5}{(q_s+1)^3}. \end{equation}\] For a long-channel transistor, \(q_s\) is simply given by \[\begin{equation} q_s = \frac{\sqrt{4 IC+1}-1}{2}. \end{equation}\]
The corresponding transfer function including the effect of the gate transcapacitance \(C_m\) is then given by \[\begin{equation} A(s) \triangleq \frac{\Delta V_{out}}{\Delta V_{in}} = A_{dc} \cdot \frac{1-s/\omega_z}{1+s/\omega_p} \end{equation}\] where \[\begin{align} A_{dc} &= -G_m \cdot R_{ds},\\ \omega_z &= \frac{G_m}{C_F+C_m},\\ \omega_p &= \frac{1}{R_{ds}\,C_{out}}, \end{align}\] with \(C_{out} = C_L+C_F\) the total load capacitance. We see that the transcapacitance \(C_m\) directly adds to the feedback capacitance \(C_F\), but does not add to the load capacitance \(C_{out}\). Therefore, the expression of the pole remains unchanged. The DC gain and the gain-bandwidth hence also remain unaffected by the transcapacitance.
The theoretical transfer function including the effect of the gate transcapacitance is shown in Figure 13. We now see that the theoretical estimation perfectly matches the simulation including at high frequency.
From Figure 13, we see that, for this long-channel transistor (\(L =\) 1 \(\mu m\)), the transcapacitance \(C_m =\) 1.346 \(fF\) is even larger than the overlap capacitance \(C_{GDo} =\) 1.057 \(fF\). This highlights the fact that if we are interested in the high-frequency behavior of a transistor, we need to account for the transcapacitance, particularly for long-channel transistors.
6 Minimum current for a given gain-bandwidth product including self-loading (short-channel)
To get the minimum current for a short-channel transistor, we simply replace the \(g_{ms}\) function by its short-channel version introducing the \(\lambda_c\) velocity saturation parameter and given by \[\begin{equation}\label{eqn:gms_short} g_{ms} = \frac{\sqrt{3 IC+1+(\lambda_c\,IC)^2} - 1}{2 + \lambda_c^2\,IC} \end{equation}\] with \(\lambda_c = L_{sat}/L\). Unfortunately there is no closed-form solution anymore. However, we can solve the same equation set numerically for finding the minimum bias current \(i_{b,opt}\) and the corresponding optimum inversion coefficient \(IC_{opt}\). The normalized current \(i_b\) is plotted versus the inversion coefficient \(IC\) in Figure 14 for a given vlue of \(\Theta\) and for different values of \(\lambda_c\). We observe that the minimum current slightly increases and the optimum inversion coefficient slightly decreases. The optimum inversion coeffcient \(IC_{opt}\) is plotted versus \(\Theta\) in Figure 15 for different values of \(\lambda_c\). It shows that the optimum \(IC\) for a short-channel device is actually quite close to the long-channel value. This shows that we can use the long-channel expression of \(IC_{opt}\) as a first guess and eventually fine tune by simulation.
7 Minimum current for a given GBW and DC gain
7.1 Analysis
We can actually use the additional degree of freedom, namely the transistor length \(L\) (which has been arbitrarily set in the previous example), to set the DC gain. To this purpose we can use the simple output conductance model given by \[\begin{equation} G_{ds} \cong \frac{I_D}{\lambda \cdot L}. \end{equation}\]
We now need to solve the following set of equations \[\begin{align} \omega_u &= \frac{G_m}{C_L} = \frac{G_m}{C_{L0} + C_{DW} \cdot W},\\ A_{dc} &= \frac{G_m}{G_{ds}} = \frac{G_m \cdot \lambda \cdot L}{I_b},\\ G_m &= \frac{I_{spec\Box}}{n U_T} \cdot \frac{W}{L} \cdot g_{ms}(IC),\\ I_b &= I_{spec\Box} \cdot \frac{W}{L} \cdot IC. \end{align}\] for \(I_b\), \(W\), \(L\) and \(G_m\). This leads to the following normalized results \[\begin{align} i_b &\triangleq \frac{I_b}{I_{norm}} = \frac{g_{ms} \cdot IC}{g_{ms}^2 - \xi \cdot IC} = \frac{g_{ms}/IC}{(g_{ms}/IC)^2 - \xi/IC},\\ w &\triangleq \frac{W}{W_{norm}} = \frac{IC}{g_{ms}^2 - \xi \cdot IC},\\ \ell &\triangleq \frac{L}{L_{norm}} = \frac{IC}{g_{ms}}, \end{align}\] where \[\begin{align} \xi &\triangleq \frac{C_{DW} \cdot (n U_T)^2}{I_{spec\Box} \cdot \lambda} \cdot A_{dc} \cdot \omega_u,\\ I_{norm} & \triangleq n\,U_T \cdot C_{L0} \cdot \omega_u,\\ W_{norm} &\triangleq \frac{C_{L0} \cdot (n U_T)^2}{I_{spec\Box} \cdot \lambda} \cdot A_{dc} \cdot \omega_u,\\ L_{norm} & \triangleq \frac{n U_T}{\lambda} \cdot A_{dc}. \end{align}\]
The normalized bias current, width and length are plotted in Figure 16, Figure 17 and Figure 18 for different values of the parameter \(\xi\).
Looking at Figure 16, we see that there is a minimum for \(\xi > 0\). The optimum value of the inversion coefficient \(IC_{opt}\) corresponding to this minimum only depends on \(\xi\) according to \[\begin{equation} IC_{opt} = \frac{\sqrt{\xi\;}}{\left(1-\sqrt{\xi\;}\right)^2} \end{equation}\] which is plotted in Figure 16 as the dashed red line. The minimum normalized current is then given by \[\begin{equation} i_{b,opt} \triangleq i_b(IC_{opt}) = \frac{1}{\left(1-\sqrt{\xi\;}\right)^2} = \frac{1+2 IC_{opt}+\sqrt{4 IC_{opt}+1}}{2}. \end{equation}\]
The optimum normalized width, length and transconductance are given by \[\begin{align} w_{opt} &\triangleq w(IC_{opt}) = \frac{1}{\sqrt{\xi\;}\;\left(1-\sqrt{\xi\;}\right)} = \frac{1+3IC_{opt}+(1+IC_{opt})\,\sqrt{4IC_{opt}+1}}{2IC_{opt}},\\ \ell_{opt} &\triangleq \ell(IC_{opt}) = \frac{1}{1-\sqrt{\xi\;}} = \frac{1+\sqrt{4IC_{opt}+1}}{2},\\ g_{m,opt} &\triangleq g_m(IC_{opt}) = \frac{1}{1-\sqrt{\xi\;}} = \frac{1+\sqrt{4IC_{opt}+1}}{2}. \end{align}\]
Note that the optimum current, width, length and transconductance only depend on \(\xi\) which brings together the technology parameters and the specs according to \[\begin{equation} \xi \triangleq \underbrace{\frac{C_{DW} \cdot (n U_T)^2}{I_{spec\Box} \cdot \lambda}}_{\textsf{technology parameters}} \cdot \underbrace{A_{dc} \cdot \omega_u}_{\textsf{specifications}}. \end{equation}\]
The optimum parameters are plotted versus \(\xi\) in Figure 19. We see that all curves tend to infinity for \(\xi \rightarrow 1\). We can therefore consider that \(\xi=1\) is an upper bound so that the product of the DC gain \(A_{dc}\) times the gain bandwidth \(\omega_u\) should satisfy the following inequality \[\begin{equation} A_{dc} \cdot \omega_u < \frac{I_{spec\Box} \cdot \lambda}{C_{DW} \cdot (n U_T)^2} \end{equation}\] This means that we can check whether the specifications on \(A_{dc}\) and \(\omega_u\) can be achieved for a given technology (i.e. for a set of \(I_{spec\Box}\), \(\lambda\) and \(C_{DW}\)). The closer \(\xi\) gets to 1, the larger the required current and size.
7.2 Design example
7.2.1 Design
We want to size a CS SC amplifier for the specifications given in Table 12. We need to find the minimum current and size the transistor to achieve this specs. We will design the amplifier for a generic 180nm bulk CMOS process. The physical parameters are given in Table 2, the global process parameters in Table 3 and finally the MOSFET parameters in Table 4.
| Specification | Symbol | Value | Unit |
|---|---|---|---|
| Gain bandwidth product | \(GBW\) | 100 | \(MHz\) |
| DC gain | \(A_{dc}\) | 50 | \(dB\) |
| Load capacitance | \(C_{{L0}}\) | 20 | \(fF\) |
We can start by checking that the specifications in Table 12 are feasible for the given 180nm technology. For this we can check that \[\begin{equation*} \xi \triangleq A_{dc} \cdot \omega_u \cdot \frac{C_{DW} \cdot (n U_T)^2}{I_{spec\Box} \cdot \lambda} < 1. \end{equation*}\] For the specifications in Table 12 and the chosen 180nm technology we have \(\xi =\) 0.023 which is much smaller than 1. We can now proceed with the calculation of the parameters including the optimum inversion coefficient, bias current, wodth and length. All the calculated parameters are presented in Table 13.
| Parameter | Value | Unit |
|---|---|---|
| \(C_{{DW}}\) | 1.167 | \(fF/\mu m\) |
| \(C_{{D0}}\) | 0.16 | \(fF\) |
| \(C_{{L0}}\) | 20 | \(fF\) |
| \(C_L\) | 20.16 | \(fF\) |
| \(\xi\) | 0.023 | - |
| \(IC_{{opt}}\) | 0.213 | - |
| \(i_{{b,opt}}\) | 1.394 | - |
| \(w_{{opt}}\) | 7.72 | - |
| \(\ell_{{opt}}\) | 1.181 | - |
| \(g_{{m,opt}}\) | 1.181 | - |
| \(\left(W/L\right)_{{opt}}\) | 3.121 | - |
| \(I_{{norm}}\) | 417 | \(nA\) |
| \(W_{{norm}}\) | 404 | \(nm\) |
| \(L_{{norm}}\) | 694 | \(nm\) |
| \(I_{{b,opt}}\) | 581 | \(nA\) |
| \(W_{{opt}}\) (effective width) | 3.12 | \(\mu m\) |
| \(L_{{opt}}\) (effective length) | 819 | \(nm\) |
| \(W\) (drawn width) | 3.08 | \(\mu m\) |
| \(L\) (drawn length) | 895 | \(nm\) |
| \(G_{{m,opt}}\) | 14.954 | \(\mu A/V\) |
| \(C_{{D,opt}}\) | 3.64 | \(fF\) |
| \(C_F\) | 1.144 | \(fF\) |
| \(C_{{out}}\) | 23.8 | \(fF\) |
| \(GBW\) (check) | 100 | \(MHz\) |
| \(f_z\) | 2.252 | \(GHz\) |
| \(A_{{dc}}\) | 50 | \(dB\) |
We see that the optimum inversion coefficient is equal to \(IC_{opt} =\) 0.213 which means that the transistor is biased in moderate inversion. The optimum bias current is the \(I_{bopt} =\) 581 \(nA\) and the required width and length are \(W =\) 3.12 \(\mu m\) and \(L =\) 819 \(nm\).
The transistor size resulting from the design are summarized in Table 14. The large- and small-signal parameters are summarized in Table 15 and Table 16.
| Transistor | \(W\;[\mu m]\) | \(L\;[\mu m]\) | \(W_{eff}\;[\mu m]\) | \(L_{eff}\;[\mu m]\) | \(W_{eff}/L_{eff}\;[-]\) |
|---|---|---|---|---|---|
| M1 | 3.12 | 0.89 | 3.16 | 0.819 | 3.859 |
| M2 | 3.12 | 0.89 | 3.16 | 0.819 | 3.859 |
| Transistor | \(I_D\;[nA]\) | \(I_{{spec}}\;[\mu A]\) | \(IC\) | \(V_G-V_{{T0}}\;[mV]\) | \(V_{{DSsat}}\;[mV]\) |
|---|---|---|---|---|---|
| M1 | 581 | 2759 | 0.210 | -27.789 | 106 |
| M2 | 581 | 2759 | 0.210 | -27.789 | 106 |
| Transistor | \(G_{{spec}}\;[\mu A/V]\) | \(G_{{ms}}\;[\mu A/V]\) | \(G_m\;[\mu A/V]\) | \(G_{{ds}}\;[nA/V]\) | \(\gamma_n\) |
|---|---|---|---|---|---|
| M1 | 106.623 | 19.043 | 14.978 | 43.271 | 0.668 |
| M2 | 106.623 | 19.043 | 14.978 | 43.271 | 0.668 |
From the parameters in Table 13 we can now plot the theoretical transfer function which is shown in Figure 20 and confirms that the specifications on the DC gain and gain-bandwidth product are met.
7.2.2 Simulations
The theoretical results can be validated by comparing them to the results obtained from simulations performed with ngspice. In order to run the simulations you need to have ngspice installed. Please refer to the ngspice instructions.
Note
The simulations are performed with ngspice [1] using the EKV 2.6 compact model [2]. For ngspice, we use the original Verilog-A implementation of EKV 2.6 [3] modified by C. Enz to get the operating point informations and available on the Gitub va-models site provided by D. Warning at [4]. The parameters correspond to a generic 180 nm bulk CMOS process [5].
Before running the AC simulation, we first need to check the quiescent voltages and currents and the operating point by running an .OP simulation. The node voltages are extracted from the .ic file and presented in Table 17.
| Node | Voltage |
|---|---|
| vdd | 1.8 |
| in | 0.440576 |
| out | 0.440576 |
| 1 | 0.440576 |
| 2 | 0.440576 |
The large-signal transistor bias information and the small-signal parameters extracted from the operating point simulation are given in Table 18 and Table 19, respectively. We see that their values are very close to the theoretical values given in Table 15 and Table 16.
| Transistor | \(I_D\;[nA]\) | \(I_{spec}\;[\mu A]\) | \(IC\) | \(n\) | \(V_{Dsat}\;[mV]\) |
|---|---|---|---|---|---|
| M1 | 581 | 2.766 | 0.210 | 1.27 | 127 |
| M2 | 581 | 2.766 | 0.210 | 1.27 | 127 |
| Transistor | \(n\) | \(G_{ms}\;[\mu A/V]\) | \(G_m\;[\mu A/V]\) | \(G_{mb}\;[\mu A/V]\) | \(G_{ds}\;[nA/V]\) |
|---|---|---|---|---|---|
| M1 | 1.27 | 18.977 | 14.727 | 4.211 | 38.443 |
| M2 | 1.27 | 18.977 | 14.727 | 4.211 | 38.443 |
The simulated transfer function is shown in Figure 22 and compared to the theoretical transfer function of Figure 20 (including the gate transcapacitance \(C_m\)).
From Figure 22 we see that the simulation perfectly matches the theoretical estimation even above the \(GBW\) thanks to the fact that we have included the transcapacitance. The simulated DC gain and \(GBW\) are slightly higher than the target.
8 Minimum current for a given input-referred thermal noise
In this section we want to answer the following question:
Question
What is the minimum current \(I_b\) and transistor size (aspect ratio \(W/L\)) in order for the OL CS gain stage to achieve a given input-referred thermal noise resistance?
The input-referred thermal noise resistance is given by \[\begin{equation*} R_{n,th}=\frac{\gamma_n}{G_m} \end{equation*}\] For a long-channel transistor, the thermal noise excess factor \(\gamma_n\) can be considered as constant and \(R_{n,th}\) decreases with \(IC\) as \(1/IC\) in WI and \(1/\sqrt{IC}\) in SI. However, when velocity saturation (VS) is considered, \(G_m\) will saturate in SI and the thermal noise excess factor \(\gamma_n\) increases with \(IC\).
We first will consider the long-channel case (no VS).
8.1 Long-channel (no VS)
In this case the thermal noise excess factor \(\gamma_n\) can be considered as constant.
We then need to solve the following set of equation for \(I_b\) and \(W/L\) \[\begin{align*} R_{n,th} &= \frac{\gamma_n}{G_m},\\ G_m &= \frac{I_{spec\Box}}{n U_T} \cdot \frac{W}{L} \cdot g_{ms}(IC),\\ I_b &= I_{spec\Box} \cdot \frac{W}{L} \cdot IC. \end{align*}\]
This leads to the following normalized results \[\begin{align} i_b &\triangleq \frac{I_b \cdot R_{n,th}}{n U_T \cdot \gamma_n} = \frac{IC}{g_{ms}},\\ AR &\triangleq \frac{W}{L} \cdot \frac{I_{spec\Box} \cdot R_{n,th}}{n U_T \cdot \gamma_n}. \end{align}\] With this normalization, the normalized current \(i_b\) and aspect ratio \(AR\) are plotted in Figure 23. Note that they are identical to the curve of the constant \(G_m\) case with \(\lambda_c=0\) shown in Figure 4.
8.2 Short-channel case (incl. VS)
When VS is present we need to account for the transconductance saturation in SI given by \(\eqref{eqn:gms_short}\) and for the dependence of \(\gamma_n\) to \(IC\) which can be approximated by [7] \[\begin{equation}\label{eqn:gamman_short} \gamma_n = \gamma_{nwi} \cdot (1 + \alpha_n \cdot IC) \end{equation}\] where \(\gamma_{nwi}\) is normally the noise excess factor in WI given by \(\gamma_{nwi} \cong n/2\). However in the empirical model \(\eqref{eqn:gamman_short}\) it is used as a fitting parameter which turns out to be very close to one. Parameter \(\alpha_n\) depends on the VS parameter \(\lambda_c\) according to \[\begin{equation} \alpha_n = \frac{n}{2} \cdot \lambda_c^2. \end{equation}\]
Eqn. \(\eqref{eqn:gamman_short}\) is plotted versus the inversion coefficient in Figure 24 for \(n =\) 1.3 and for different values of \(\lambda_c\) and hence of \(\alpha_n\).
The normalized input-referred thermal noise resistance can be defined as \[\begin{equation} r_n \triangleq R_{n,th} \cdot G_{spec} = \frac{\gamma_n}{g_m} \end{equation}\] with \(g_m \triangleq G_m/G_{spec}\).
To find the current for achieving a given input-referred thermal noise resistance, we need to solve the following set of equations for \(I_b\) and \(W/L\) \[\begin{align} R_{nt} &= \frac{\gamma_n}{G_m},\\ \gamma_n &= \gamma_{nwi} \cdot (1 + \alpha_n \cdot IC),\\ G_m &= \frac{I_{spec\Box}}{n U_T} \cdot \frac{W}{L} \cdot g_{ms}(IC),\\ I_b &= I_{spec\Box} \cdot \frac{W}{L} \cdot IC, \end{align}\]
This leads to the following normalized results \[\begin{align} i_b &\triangleq \frac{I_b \cdot R_{n,th}}{n U_T \cdot \gamma_{nwi}} = \frac{IC}{g_{ms}} \cdot (1+\alpha_n \cdot IC),\\ AR &\triangleq \frac{W}{L} \cdot \frac{I_{spec\Box} \cdot R_{n,th}}{n U_T \cdot \gamma_{nwi}} = \frac{1}{g_{ms}}\cdot (1+\alpha_n \cdot IC). \end{align}\] \(i_b\) is plotted versus \(IC\) in Figure 25 for various values of \(\lambda_c\). We see that things have become worse in SI. We need much more current to achieve the same input-referred thermal noise resistance as \(\lambda_c\) increases. As the inversion coefficient increases, the normalized source transconductance saturates to \(1/\lambda_c\) and therefore the normalized current increase with \(IC\) according to \[\begin{equation} i_b \cong \lambda_c \cdot \alpha_n \cdot IC^2 = \frac{n}{2} \cdot \lambda_c^3 \cdot IC^2. \end{equation}\] For example for \(\lambda_c = 0.5\), this means that we need 100 times more current for \(IC=100\) compared to the long-channel case (\(\lambda_c = 0\)). Clearly, WI gives the smallest bias current. However this leads to a large transistor.
This can be evaluated by looking at the normalized aspect ratio \(AR\) which is plotted versus \(IC\) in Figure 26 for the same values of \(\lambda_c\). As for the long-channel case, we see that \(AR\) increases as \(1/IC\) when moving to WI. In SI and under VS, \(AR\) increases instead of decreasing as \(1/\sqrt{IC}\) as it does for \(\lambda_c=0\). In SI under VS \(1/g_{ms}=\lambda_c\) and hence \(AR\) increases as \[\begin{equation} AR \cong \lambda_c \cdot \alpha_n \cdot IC = \frac{n}{2} \cdot \lambda_c^3 \cdot IC. \end{equation}\] We also see that there is a minimum of \(AR\) and therefore a minimum width for a given length.
9 Minimum input-referred thermal noise (short-channel)
Note
Note that in this section we look at the input-referred thermal noise resistance versus the inversion coefficient instead of the bias current for a given input-referred thermal noise resistance.
We have seen that for a short-channel transistor the thermal noise excess factor increases with \(IC\) in SI. According to \(\eqref{eqn:gamman_short}\), in very SI under heavy VS the thermal noise excess factor is given by \(\gamma_n \cong \gamma_{wi} \cdot \alpha_n \cdot IC\) and the normalized transconductance \(g_m\) saturates to \(g_m \cong 1/(n\,\lambda_c)\) so that the normalized thermal noise resistance \(r_n\) now increases with \(IC\) according to \[\begin{equation} r_n \cong \gamma_{nwi} \cdot \frac{n^2}{2} \cdot \lambda_c^3 \cdot IC \cong \frac{n^2}{2} \cdot \lambda_c^3 \cdot IC \quad \textsf{in SI and sat.} \end{equation}\] On the other hand, in WI, \(\gamma_{nwi}\) is constant (close to one) and \(g_m\) is proportionnal to \(IC\) according to \(g_m \cong IC/n\). The normalized input-referred white noise resistance decreases with respect to \(IC\) improving the noise according to \[\begin{equation} r_n \cong \gamma_{nwi}\,\frac{n}{IC} \cong \frac{n}{IC} \quad \textsf{in WI and sat.} \end{equation}\]
Since the normalized input-referred white noise resistance \(r_n\) decreases as \(1/IC\) in WI and inceases as \(IC\) in SI, it reaches a minimum in moderate inversion (MI). There is no simple closed form expression of the optimum \(IC\) for which \(r_n\) reaches a minimum. However we can find an approximation by equating the two asymptotes and solving for \(IC\). This gives an approximate value of the optimum inversion coefficient \[\begin{equation} IC_{opt} \cong \sqrt{\frac{2}{n \cdot \lambda_c^3}}. \end{equation}\]
The normalized input-referred thermal noise resistance \(r_n\) in saturation is plotted versus the inversion coefficient \(IC\) for an nMOS transistor from a 40nm bulk CMOS technology in Figure 27. We clearly see that there is a minimum on the upper side of moderate inversion. The estimation of the optimum inversion coefficient is slightly lower than the value corresponding to the effective minimum. However, considering the log scale used for the x-axis and the empiricial model used, this estimation is good enough.
This result is particularly important for RF IC design where white noise is dominating in low-noise amplifiers (LNAs). Note that an additional gate resitance needs to be added to the input-referred noise resistance [6].
Now that we have found the optimum inversion coefficient for achieving a minimum input-referred thermal noise resistance, we can find the corresponding \(W/L\) and bias current \(I_b\) according to \[\begin{align} \left.\frac{W}{L}\right|_{opt} &= r_{n,min} \cdot \frac{U_T}{R_{n,th}\,I_{spec\Box}},\\ I_b &= I_{spec\Box} \cdot \left.\frac{W}{L}\right|_{opt} \cdot IC_{opt} = r_{n,min} \cdot \frac{U_T}{R_{n,th}} \cdot IC_{opt}. \end{align}\] where \(r_{n,min} = r_n(IC_{opt})\).
Note
The fact that the input-referred thermal noise resistance (or white noise power spectral density or PSD) gets minimum for an optimum value of the inversion coefficient often located on the upper side of moderate inversion does not mean that it is achieved with a minimum bias current. It simply means that for a given current budget, we can find an optimum value of the inversion coefficient for which the input-referred thermal noise resistance gets minimum.
10 Minimum of \(F_{min}\) (short-channel)
It can be shown that the minimum noise factor accounting for the effects of the gate resistance and the induced-gate noise (but without the correlation) can be approximated by [6] \[\begin{equation} F_{min} \cong 1 + 2\frac{\gamma_n}{G_m} \, \omega \, C_{GS} \, \sqrt{\alpha_G + b_n}, \end{equation}\] where \(C_{GS}\) is the gate-to-source capacitance, \(b_n=2/(5n^2)\) and \(\alpha_G\) is the thermal noise contribution of the gate resistance normalized to that of the channel \[\begin{equation} \alpha_G \triangleq \frac{R_G}{\gamma_n/G_m}. \end{equation}\]
In RF we often use minimum length devices. In this case the gate-to-source capacitance is dominated by the extrinsic capacitance made of the overlap and fringing field capacitances. It scales with the width according to \(C_{GS} \cong W \cdot C_{GeW}\) where \(C_{GeW}\) is the total extrinsic capacitance per unit width. We can then rewrite the minimum noise factor as \[\begin{equation} F_{min} \cong 1 + 2\frac{\gamma_n}{g_{ms}} \, \frac{\omega}{\omega_n} \, \sqrt{\alpha_G + b_n} \end{equation}\] where \[\begin{equation} \omega_n \triangleq \frac{I_{spec\Box}}{n U_T \,L_f\,C_{GeW}} \end{equation}\]
The minimum noise figure \(NF_{min}\) is plotted versus \(IC\) in Figure 28 for two different operating frequencies in the case of an nMOS transistor from a 40nm bulk CMOS process. The transistor is rather large since it is made of \(M=10\) devices with \(N_f=10\) fingers and a finger width \(W_f=1.8\,\mu m\) and a finger length \(L_f=40\,nm\). We clearly see the minimum which occurs for the same value of \(IC\) than the input-referred thermal noise resistance. The larger the frequency the larger the minimum figure.
11 Conclusion
In this notebook we have analyzed the basic common-source (CS) gain stage in open-loop (OL) configuration. We started by looking at the minimum current for achieving a given transconductance and gain-bandwidth product with a constant load capacitance, which turns out to be in weak inversion. Then we accounted for the self-loading capacitance at the drain which introduces a minimum in the bias current for achieving a given gain-bandwidth product for a given transistor length. We then used the additional degree of freedom, namely the transistor length, for at the time also achieving a given DC gain. We have shown that there is an optimum inversion coefficient leading to a minimum current for achieving at the same time a given DC gain and gain-bandwidth product. The theory was then illustrated by an example designed for a 180nm generic technology. The results have been validated by simulation with ngspice [1] using the EKV 2.6 compact model [2] [3].
We then looked at the bias current required for achieving a given input-referred thermal noise resistance, which again turns out to be in weak inversion. We also have seen that, for short-channel transistors, the required current increases significantly in strong inversion compared to the long-channel case because of the effect of velocity saturation.
Finally, we had a look at the input-referred thermal noise resistance versus the inversion coefficient for a short-channel device. We discovered that there is an optimum inversion coefficient for which the input-referred thermal noise resistance bcomes minimum. Similarly, we also have shown that there is an optimum inversion coefficient for which the minimum noise factor becomes minimum for a short-channel transistor at a given operating frequency.
Note
Note that CS gain stages are seldom used in open-loop configuration. They usually include some feedback such as a feedback capacitor like in switched-capacitor circuits. The above theory is extended in another notebook to a closed-loop gain stage with capacitive feedback.
12 References
[1]
Holger Vogt, Giles Atkinson, Paolo Nenzi, “Ngspice User’s Manual Version 43.” https://ngspice.sourceforge.io/docs/ngspice-43-manual.pdf, 2024.
[2]
M. Bucher, C. Lallement, C. Enz, F. Théodoloz, and F. Krummenacher, “The EPFL-EKV MOSFET Model Equations for Simulation.” https://github.com/chrisenz/EKV/blob/main/EKV2.6/docs/ekv_v26_rev2.pdf, 1998.
[3]
W. Grabinski et al., “FOSS EKV2.6 verilog-a compact MOSFET model,” in European solid-state device research conference (ESSDERC), 2019, pp. 190–193. doi: 10.1109/ESSDERC.2019.8901822.
[4]
Dietmar Warning, “Verilog-A Models for Circuit Simulation.” https://github.com/dwarning/VA-Models, 2024.
[5]
W. Grabinski et al., “FOSS EKV 2.6 parameter extractor,” in 2015 22nd international conference mixed design of integrated circuits & systems (MIXDES), 2015, pp. 181–186. doi: 10.1109/MIXDES.2015.7208507.
[6]
C. C. Enz and E. A. Vittoz, Charge-Based MOS Transistor Modeling - The EKV Model for Low-Power and RF IC Design, 1st ed. John Wiley, 2006.
[7]
C. Enz, “Simple Expression of the Thermal Noise Excess Factor for LNA Design,” in 2022 29th IEEE international conference on electronics, circuits and systems (ICECS), 2022, pp. 1–4.